[7-3]Cache-Aware Scheduling and Analysis for Multicores

Date:2009-07-02

Title: Cache-Aware Scheduling and Analysis for Multicores
Speaker: Professor Wang Yi, Uppsala University, Sweden
Time: 4pm, Friday July 3
Venue: Lecture room, Lab for Computer Science, Level 3 Building #5, ISCAS

ABSTRACT
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms; the way of handling the on-chip shared resources such as L2 cache may have a signi cant impact on the timing predictability. In this paper, we propose to use cache space isolation techniques to avoid cache contention for hard real-time tasks running on multicores with shared caches. We present a scheduling strategy for real-time tasks with both timing and cache space constraints, which allows each task to use a xed number of cache partitions, and makes sure that at any time a cache partition is occupied by at most one running task. In this way, the cache spaces of tasks are isolated at run-time.

As technical contributions, we present solutions for the scheduling analysis problem. For simplicity, the presentation will focus on non-preemptive xed-priority scheduling. However our techniques can be easily adapted to deal with other scheduling strategies like EDF.We have developed a sufficient schedulability test for non-preemptive xed-priority scheduling for multicores with shared L2 cache, encoded as a linear programming problem. To improve the scalability of the test, we then develop our second schedulability test of quadratic complexity, which is an over approximation of the rst test. To evaluate the performance and scalability of our techniques, we use randomly generated task sets. Our experiments show that the rst test which employs an LP solver can easily handle task sets with thousands of tasks in minutes using a desktop computer.

It is also shown that the second test is comparable with the rst one in terms of precision, but scales much better due to its low complexity, and is therefore a good candidate for efficient schedulability tests in the design loop for embedded systems or as an on-line test for admission control.