Seminar Announcement 

　　Title: Synthesis of Timed Admission Controllers 

　　Speaker: Shaofa Yang (Inst. of Software, CAS) 

　　Time: 10th July 2015, 15:00 

　　Venue: __Room 337___, Level 3, Building 5,  Institute of Software, CAS 

　　Abstract: 

　　In many real-time computing environments, there are some tasks that are time-critical and others that are not. To ensure that every critical task is completed before its deadline, it may be necessary to deny entry into the ready queue for some non-critical tasks. We address this problem in the framework of controller synthesis.  Our goal is to come up with an admission controller which admits or rejects  a task request, so that no admitted task misses its deadline and the admitted patterns of task releases satisfy an LTL specification. We show that it is decidable to determine if such an admission controller exists. Further, if the answer is positive, it is possible to effectively construct a controller in the form of a finite timed automaton. 

　　This is joint work with P.S. Thiagarajan and Wang Yi.